1. Field of the Invention
This invention relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus including an output CMOS (complementary metal oxide semiconductor) circuit.
2. Background Art
As conventionally known in the art, in a semiconductor apparatus, a CMOS circuit can be provided as an output circuit for externally extracting an output signal of the internal circuit. The CMOS circuit comprises a P-channel MOSFET (metal oxide semiconductor field effect transistor) and an N-channel MOSFET. The source of the P-channel MOSFET is connected to the high-potential power supply line (VDD) of the semiconductor apparatus, and the source of the N-channel MOSFET is connected to the low-potential power supply line (VSS). The output signal of the internal circuit is applied to the gates of these MOSFETs, and their drains are connected to the output terminal of the semiconductor apparatus. Thus, in response to the output signal of the internal circuit, the VDD potential or the VSS potential is applied to the output terminal (see, e.g., JP-A H5-003173(Kokai) (FIG. 11)).
In such a semiconductor apparatus, to protect a MOSFET of the CMOS circuit from ESD (electrostatic discharge) applied to the output terminal, an ESD protection device can be connected in parallel to the MOSFET between the output terminal and the high-potential power supply line or between the output terminal and the low-potential power supply line, as also known in the art. This ESD protection device is illustratively based on a MOSFET. For example, to protect the N-channel MOSFET (hereinafter referred to as “output NMOS”) constituting the CMOS circuit, an N-channel MOSFET (hereinafter referred to as “protection NMOS”) is connected in parallel to this output NMOS between the output terminal and the low-potential power supply line. The gate of this protection NMOS is connected to the low-potential power supply line so that the protection NMOS is normally on and is turned off upon application of ESD to the output terminal (see, e.g., JP-A 2007-096211(Kokai) (FIG. 9)).
However, this type of semiconductor apparatus has the following problem. The gate of the protection NMOS is constantly subjected to the potential of the low-potential power supply (VSS potential), and is completely in the OFF state. In contrast, the gate of the output NMOS is subjected to an indefinite potential between the VDD potential and the VSS potential by the internal circuit, and hence induces a channel as compared with the protection NMOS. Hence the drain-source voltage for turning on the output NMOS is lower than the drain-source voltage for turning off the protection NMOS. Thus, upon application of ESD to the output terminal, the output NMOS is turned on earlier than the protection NMOS, and the flow of ESD current unfortunately concentrates on the output NMOS. Hence, simply connecting the protection NMOS in parallel to the output NMOS does not achieve a sufficient protection effect. Depending on the magnitude of the applied ESD current, the output NMOS may be broken down.